The present invention relates generally to computer architectures and operational processes. More particularly, the invention is directed to systems and methods for performing non-predictive pattern data transfers in the context of a computer architecture utilizing a data cache and a system memory.
Contemporary designs of workstation computers utilize architectures which include one or more high speed cache type memories. Such cache memories are used to offset the effects of the relational low speed system memories. U.S. Pat. No. 4,719,568 describes the structure and use of a now classic workstation employing cache memories for both data and instructions.
It is also common for contemporary workstations to be architected with multiple buses, the prevailing practice including both a system bus and an input-output (I/O) bus. The I/O bus communicates information between the workstation and units functionally external to the workstation. A well known example of an I/O bus is the Micro Channel* bus which appears in the Personal System/2* and RISC System/6000* product lines available from IBM Corporation. The Micro Channel bus employs a bus master/slave protocol which is also widely understood and utilized. FNT *Trademark of IBM Corporation
Another aspect of such conventional workstation architectures involves the prevalent use of direct memory access (DMA) resources. DMA enables direct data transfers between the I/O bus and the system memory, thereby avoiding the transfer of each data word through the processor. DMA practices are well known by those skilled in computer technologies.
Data integrity requires that any write operations ensure consistency between the corresponding data in cache and system memory. The preferred solution has involved the use of the cache as the access medium for write operations. Thus, all write type transfers of data to system memory are through the cache memory, ensuring data correspondence.
The size of the block of data written to a cache, whether that be from the I/O bus to an I/O cache by the DMA resources or directly from the processor to the processor cache, is not predictable. Therefore, the data to be transferred may or may not fill the whole transfer unit of the cache during any one transfer cycle. Given such unpredictability and the pervasive need for data integrity, common practice involves a transfer sequence beginning with a read of preexisting data from system memory into the cache, followed by a selective write of the modifying data into the cache, and concluded with a transfer of the composite data from cache back to the system memory. The last step is usually deferred until a cache miss occurs during a succeeding data write cycle. Thereby, irrespective of how much cache data changes as a consequence of the cache write cycle, the unchanged portion of the data unit in the cache, typically a cache line, must be returned to system memory as originally stored in system memory during the eventual cache line write to system memory cycle.
The practice of reading a cache line of data from system memory into the cache, writing data changes into the cache by a processor or DMA resources, and the eventual transfer of the composite cache line data back to system memory is slow. Reading from system memory prior to writing into cache is particularly undesirable, in that the read of the system memory RAM is significantly slower than a corresponding write operation. Furthermore, the succession of a write operation from cache to the system,memory followed immediately by a system memory read operation, for the next cache line, monopolizes the high speed system bus for relatively long intervals of time.
In the context of a computer architecture having both cache and system memory functions, there remains a need for a system and method by which non-predictive pattern data transfers to cache can be accomplished without compromising the data integrity or unduly monopolizing the processor bus.